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B. MANJURATHI1, R. HARIKUMAR RAJAGURU2
- Assistant Professor, Department of Electronics and Communication Engineering, Karunya University, Coimbatore, India
- Professor, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, India
System on chip is the major challenging issue for both design engineers and testing engineers due to its high power consumption. During testing, the volume of the test data is extremely high when compared to normal mode and because of that the switching activity which takes place between the test vectors leads to increase in power consumption. The Proposed technique is the combination of hamming distance based reordering, Bit stuffing and encoding for the original test patterns. It improves the compression ratio and also gives reduction in Average, peak power of MINTEST test sets of ISCAS’89 benchmark circuits..
Column wise bit filling technique, Hamming distance, Reordering, Multiple run length code technique, Selective Huffman encoding, Power reduction, VLSI.
Submitted at: Oct. 10, 2015
Accepted at: Feb. 10, 2016
B. MANJURATHI, R. HARIKUMAR RAJAGURU, Analysis of test data compression and power reduction using multiple encoding for Opto Electronic circuits, Journal of Optoelectronics and Advanced Materials Vol. 18, Iss. 1-2, pp. 112-117 (2016)
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