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SWATI SHARMA1,* , DEEPIKA2
- Department of Electrical Engineering,Dronacharya College of Engineering, Farrukhnagar, Gurugram, India
- Department of Applied Sciences, Dronacharya College of Engineering, Farrukhnagar, Gurugram, India
Due to rapid miniaturization of MOS structures in integrated circuits, it is necessary to improve the MOS efficiency for future device applications. The MOS capacitor can survive 3-10 K-Rad Silicon atomswithout any parametric dilapidation. In this paper,Al/SiO2/p-Si MOS capacitor wasfabricated and characterized usingcapacitance-voltage (C-V),conductance-voltage(G-V)and Resistance-voltage (R-V)measurements.The oxide thickness of p-Si MOS Capacitor was found to be50nm. The MOSstructure was fabricatedusingdry oxidationand thermal evaporation method. All electrical characteristicswere recorded on LCR Hi-Testerand the theoreticalcalculations have been doneusing MATLAB.The highquality Al/SiO2interface isverified by C-V,G-V and R-V curves. The arbitrary bias conditions have been predicted using electrical characterization such asthe flat band voltages in terms of interface trap charges and the threshold Voltage.They show asharp transition from depletion to accumulation with “zero” hysteresis. The C-V and G-V plots show better efficiency of fabricated MOS capacitor. In R-V characteristics, resistance invariably decreaseexponentiallythus the depth of depletionregion is high..
MOS capacitor, Capacitance, Trans-conductance, Interface trap charges, Flat band Voltage.
Submitted at: Nov. 6, 2019
Accepted at: Dec. 7, 2020
SWATI SHARMA, DEEPIKA, Performance analysis using electrical characteristics ofAl/SiO2 /p-Si based MOS device, Journal of Optoelectronics and Advanced Materials Vol. 22, Iss. 11-12, pp. 590-595 (2020)
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